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NB100LVEP91 2.5 V/3.3 V Any Level Positive Input to -2.5 V/-3.3 V LVNECL Output Translator
Description
http://onsemi.com MARKING DIAGRAMS*
20
20 1
The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential LVNECL output signals (-2.5 V / -3.3 V). To accomplish the level translation the LVEP91 requires three power rails. The VCC pins should be connected to the positive power supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low state, and Q outputs to a high state, which will ensure stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, www..com decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
Features
NB100LVEP91 AWLYYWWG
SO-20 WB DW SUFFIX CASE 751D
1
24 1
24 1
24 PIN QFN MN SUFFIX CASE 485L A WL, L YY, Y WW, W G or G
N100 VP91 ALYWG G
* * * * * *
Maximum Input Clock Frequency > 2.0 GHz Typical Maximum Input Data Rate > 2.0 Gb/s Typical 500 ps Typical Propagation Delay Operating Range: VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GND = 0 V Q Output will Default LOW with Inputs Open or at GND Pb-Free Packages are Available*
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
(Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 13
1
Publication Order Number: NB100LVEP91/D
NB100LVEP91
Positive Level Input D0 R1 D0 R1 D1 R1 D1 R1 D2 R1 D2 R1 NECL Output Q0 R2 Q0
Q1 R2 Q1 VCC VBB GND Q2 R2 Q2 VEE
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
Pin SOIC 1, 20 QFN 3, 4, 12 Name VCC I/O - Default State - Description Positive Supply Voltage. All VCC Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. Ground. ECL Reference Voltage Output Noninverted Differential Inputs [0:2]. Internal 75 kW to VEE. Inverted Differential Inputs [0:2]. Internal 75 kW to VEE and 75 kW to VCC. When Inputs are Left Open They Default to (VCC - VEE) / 2. Noninverted Differential Outputs [0:2]. Typically Terminated with 50 W to VTT = VCC - 2 V Inverted Differential Outputs [0:2]. Typically Terminated with 50 W to VTT = VCC - 2 V No Connect. The NC Pin is NOT Electrically Connected to the Die and may Safely be Connected to Any Voltage from VEE to VCC. Exposed Pad. (Note 1)
10
15, 16
VEE
-
-
14, 17 4, 7 2, 5, 8 3, 6, 9
19, 20, 23, 24 7, 11 5, 8, 13 6, 9, 14
GND VBB D[0:2] D[0:2]
- - LVPECL, LVDS, LVTTL, LVCMOS, CML, HSTL Input LVPECL, LVDS, LVTTL,LVCMOS, CML, HSTL Input LVNECL Output LVNECL Output -
- - Low High
19,16,13 18,15,12 11
2, 18, 22 1, 21, 17 10
Q[0:2] Q[0:2] NC
- - -
N/A
-
EP
-
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat-sinking conduit.
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NB100LVEP91
GND GND Q1 24 Q0 VCC Q0 20 19 Q0 GND Q1 Q1 GND Q2 18 17 16 15 14 13 Q2 NC 12 11 Q0 VCC VCC NB100LVEP91 D0 D0 1 VCC 2 D0 3 4 5 6 7 8 9 D2 10 VEE 1 2 3 4 5 6 7 VBB 8 D1 9 D1 10 11 12 VCC NB100LVEP91 23 22 Q1 GND GND 21 20 19 18 17 16 15 14 13 Q2 Q2 VEE VEE D2 D2 Exposed Pad (EP)
D0 VBB D1
D1 VBB D2
NC VBB
Figure 2. SOIC-20 Lead Pinout (Top View)
Figure 3. QFN-24 Lead Pinout (Top View)*
*All VCC, VEE and GND pins must be externally connected to a power supply and the underside exposed pad must be attached to an adequate heat-sinking conduit to guarantee proper operation.
Table 2. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection (R1) (R2) Human Body Model Machine Model Charged Device Model Pb Pkg SO-20 WB QFN-24 Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 2. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 Level 1 Level 1 Value 75 kW 75 kW > 2 kV > 150 V > 2 kV Pb-Free Pkg Level 3 Level 1
Moisture Sensitivity (Note 2)
UL 94 V-0 @ 0.125 in 446 Devices
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NB100LVEP91
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI VOP Iout IBB TA Tstg qJA qJA qJC Tsol Positive Power Supply Negative Power Supply Positive Input Voltage Operating Voltage Output Current PECL VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) JESD 51-3 (1S-Single Layer Test Board) Thermal Resistance (Junction-to-Ambient) JESD 51-6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm 0 lfpm 500 lfpm Standard Board SOIC-20 SOIC-20 QFN-24 QFN-24 SOIC-20 QFN-24 Parameter Condition 1 GND = 0 V GND = 0 V GND = 0 V GND = 0 V Continuous Surge VI VCC VCC - VEE Condition 2 Rating 3.8 to 0 -3.8 to 0 3.8 to 0 7.6 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 37 32 30 to 35 11 225 225 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 4. DC CHARACTERISTICS POSITIVE INPUTS VCC = 2.5 V, VEE = -2.375 to -3.8 V, GND = 0 V (Note 3)
-40C Symbol ICC VIH VIL VIHCMR IIH IIL Characteristic Positive Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) D D 0.5 -150 Min 10 1335 GND 0 Typ 14 Max 20 VCC 875 2.5 150 0.5 -150 Min 10 1335 GND 0 25C Typ 14 Max 20 VCC 875 2.5 150 0.5 -150 Min 10 1335 GND 0 85C Typ 14 Max 20 VCC 875 2.5 150 Unit mA mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / -0.125 V. 4. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
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NB100LVEP91
Table 5. DC CHARACTERISTICS POSITIVE INPUT VCC = 3.3 V; VEE = -2.375 V to -3.8 V; GND = 0 V (Note 5)
-40C Symbol ICC VIH VIL VBB VIHCMR IIH IIL Characteristic Positive Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) PECL Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) D D 0.5 -150 Min 10 2135 GND 1775 0 1875 Typ 16 Max 24 VCC 1675 1975 3.3 150 0.5 -150 Min 10 2135 GND 1775 0 1875 25C Typ 16 Max 24 VCC 1675 1975 3.3 150 0.5 -150 Min 10 2135 GND 1775 0 1875 85C Typ 16 Max 24 VCC 1675 1975 3.3 150 Unit mA mV mV mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / -0.925 V. 6. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
Table 6. DC CHARACTERISTICS NECL OUTPUT VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GND = 0 V (Note 7)
-40C Symbol IEE VOH VOL Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Min 40 -1145 -1945 Typ 50 -1020 -1770 Max 60 -895 -1600 Min 38 -1145 -1945 25C Typ 50 -1020 -1770 Max 68 -895 -1600 Min 38 -1145 -1945 85C Typ 50 -1020 -1770 Max 68 -895 -1600 Unit mA mV mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Output parameters vary 1:1 with GND. 8. All loading with 50 W resistor to GND - 2.0 V.
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NB100LVEP91
Table 7. AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -3.8 V; GND = 0 V
-40C Symbol VOUTPP Characteristic Output Voltage Amplitude (Figure 4) (Note 9) Propagation Delay D to Q Pulse Skew (Note 10) Output-to-Output (Note 11) Part-to-Part (Diff) (Note 11) RMS Random Clock Jitter (Note 12) fin = 2.0 GHz Peak-to-Peak Data Dependant Jitter fin = 2.0 Gb/s (Note 13) Input Voltage Swing (Differential Configuration) (Note 14) Output Rise/Fall Times @ 50 MHz (20% - 80%) Q, Q 200 75 fin v 1.0 GHz fin v 1.5 GHz fin v 2.0 GHz Differential Single-Ended Min 575 525 300 375 300 Typ 800 750 600 500 450 15 25 50 0.5 20 800 150 600 650 75 95 125 2.0 Max Min 600 525 250 375 300 25C Typ 800 750 550 500 450 15 30 50 0.5 20 200 75 800 150 600 675 75 105 125 2.0 Max Min 550 400 150 400 300 85C Typ 800 750 500 550 500 15 30 70 0.5 20 200 75 800 150 650 750 80 105 150 2.0 Max Unit mV
tPLH tPHL0 tSKEW
ps ps
tJITTER
ps
VINPP tr, tf
1200 250
1200 250
1200 275
mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to GND - 2.0 V. Input edge rates 150 ps (20% - 80%). 10. Pulse Skew = |tPLH - tPHL| 11. Skews are valid across specified voltage range, part-to-part skew is for a given temperature. 12. RMS Jitter with 50% Duty Cycle Input Clock Signal. 13. Peak-to-Peak Jitter with input NRZ PRBS 231-1 at 2.0 Gb/s. 14. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of 50. 850 OUTPUT VOLTAGE AMPLITUDE (mV) 750 650 550 450 350 RMS JITTER 250 0.5 1.0 1.5 2.0 10 9.0 AMP 8.0 6.0 5.0 4.0 3.0 2.0 1.0 0 2.5 RMS JITTER (ps) 7.0
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin) at Ambient Temperature (Typical)
D VINPP = VIH(D) - VIL(D) D Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 5. AC Reference Measurement http://onsemi.com
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NB100LVEP91
Application Information
All NB100LVEP91 inputs can accept LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signal levels. The limitations for differential input signal (LVDS, HSTL, LVPECL, or CML) are the minimum input swing of 150 mV
VCC VCC
and the maximum input swing of 3.0 V. Within these conditions, the input voltage can range from VCC to GND. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W)
VCC VCC
Z LVPECL Driver Z 50 W GND 50 W
D LVEP91 D LVDS Driver
Z 100 W Z
D LVEP91 D
VTT = VCC - 2.0 V
GND
VEE
GND
GND
VEE
Figure 6. Standard LVPECL Interface
VCC VCC VCC
Figure 7. Standard LVDS Interface
VCC VCC
50 W Z HSTL Driver Z 50 W GND GND 50 W GND VEE GND D D LVEP91 CML Driver Z Z
50 W D LVEP91 D
GND
VEE
Figure 8. Standard HSTL Interface
VCC VCC
Figure 9. Standard 50 W Load CML Interface
VCC VCC
Z LVTTL Driver 1.5 V (externally generated reference voltage) GND
D LVEP91 D LVCMOS Driver
Z
D LVEP91
Open
D
GND
VEE
GND
GND
VEE
Figure 10. Standard LVTTL Interface
Figure 11. Standard LVCMOS Interface (D will default to VCC/2 when left open. A reference voltage of VCC/2 should be applied to D input, if D is interfaced to CMOS signals.) http://onsemi.com
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NB100LVEP91
ORDERING INFORMATION
Device NB100LVEP91DW NB100LVEP91DWG NB100LVEP91DWR2 NB100LVEP91DWR2G NB100LVEP91MN NB100LVEP91MNG NB100LVEP91MNR2 NB100LVEP91MNR2G Package SO-20 SO-20 (Pb-Free) SO-20 SO-20 (Pb-Free) QFN-24 QFN-24 (Pb-Free) QFN-24 QFN-24 (Pb-Free) Shipping 38 Units / Rail 38 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 92 Units / Rail 92 Units / Rail 3000 / Tape & Reel 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = GND - 2.0 V
Figure 12. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB100LVEP91
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1 10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
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NB100LVEP91
PACKAGE DIMENSIONS
QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O
D
PIN 1 IDENTIFICATION
A
B
E
2X
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45
0.15 C
2X
0.15 C A2 0.10 C A
0.08 C
SEATING PLANE
A1 D2 L
7 6
A3
REF
C
DIM A A1 A2 A3 b D D2 E E2 e L
e
12 13
E2
24X
b
1 24 19
18
0.10 C A B 0.05 C
e
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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NB100LVEP91/D

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